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LH5PV16256 cmos 4m (256k 16) pseudo-static ram features 262,144 words 16 bit organization power supp ly: +3.0 0.15 v access time: 120 ns (max.) cycle time: 190 ns (min.) power consumption (max.): 126 mw (operating) 94.5 m w (standby = cmos input l evel) 220.5 m w (self-refresh = cmos input l evel) lvttl compatible i/o available for a ddress refresh, auto-refresh, and self-refresh modes 2,048 refresh cycles/32 ms address non-multiple available for byte write mode using uwe and lwe pins package: 44-pin, tsop (type ii) process: silicon-g ate cmos operating temperatu re: 0 - 70 c not de signed or rated as radiation hardened desc ription the lh 5pv16256 is a 4m bit pseudo-static ram with a 262,144 words 16 bit or gani zation. pin connections 2 3 4 5 6 9 10 7 8 uwe 11 1 44 43 42 41 38 37 40 39 36 35 gnd i/o 15 44-pin tsop (type ii) 12 15 13 14 33 32 34 31 30 lwe a 1 a 0 a 3 a 4 v cc v cc i/o 6 i/o 13 i/o 14 i/o 11 i/o 12 i/o 10 i/o 9 rfsh i/o 7 i/o 5 5pv16256s-1 a 5 a 17 cs a 16 a 15 a 14 a 13 17 18 19 20 21 22 a 11 16 29 28 27 26 23 25 24 i/o 3 a 12 a 9 a 10 ce i/o 1 i/o 2 oe i/o 0 gnd a 2 a 6 a 8 a 7 i/o 4 i/o 8 top view figure 1. pin connections 1
pin description pin name function a 7 - a 17 row address input a 0 - a 6 column address input uwe, lwe upper/lower write enable input oe output enable input rfsh refresh input ce chip enable input pin name function cs chip select input i/o 8 - i/o 15 upper byte data input/output i/o 0 - i/o 7 lower byte data input/output v cc power supply gnd ground i/o 1 clock generator cs a 5 a 4 a 3 a 10 a 11 a 12 a 13 a 14 a 15 a 16 a 6 a 17 a 9 a 8 a 7 column address buffer row address buffer refresh address counter data in buffer data out buffer i/o selector column decoder sense amps memory array 8m row decoder ext/int address mux. refresh controller refresh timer i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 v bb generator gnd v cc a 2 a 1 5pv16256s-2 i/o 0 rfsh oe 21 20 19 18 17 16 15 14 13 12 10 9 8 7 6 5 4 11 33 24 44 35 25 26 27 28 29 30 31 32 ce 22 a 0 3 lwe uwe 2 1 a 0 - a 6 a 7 - a 17 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 i/o 8 36 37 38 39 40 41 42 43 gnd 23 v cc 34 figure 2. lh 5pv16 256 block diagram LH5PV16256 cmos 4m (256 16) pseudo-st atic ram 2
truth table ce cs rfsh oe uwe lwe mode i/o 0 - 7 i/o8 - 15 l h h l h h word read output data output data lh h x hl write lower byte write input data dont care l h upper byte write dont care input data l l word write input data input data h h invalid high-z high-z h x l x x x auto refresh high-z high-z l l h x x x cs standby high-z high-z h x h x x x standby high-z high-z notes: h = high l = low x = dont care requirements 2 we control please do not separate the uwe and lwe operation timing intentionally in the same write cycles. each of the uwe/ lwe should satisfy the timing specifications individually. refresh after self-refresh or data retention mode if address refresh is used during normal read/write cycles, the first address refresh must be executed within 15 m s after self-refresh or data retention mode ends and the addr ess refresh must be executed conti nuously for 2,048 refresh cycles. if distributed auto-refresh is used during normal read/write cycles, the first auto-refresh must be executed within 15 m s after self-refresh or data retention mode ends. if burst auto-refresh is used during normal read/write cycles, the first auto-refresh must be executed within 15 m s after self-ref resh or data retention mode ends, and the auto-refresh must be executed continuously for 2,048 refresh cycles. bypass capacitor for power supply noise reduction because a psram operates dynamically like a dram, it is recommended to put bypass capacitors between v cc and gnd to absorb power supply noise due to the peak current. cmos 4m (256 16) pseudo-static ram lh 5pv16256 3
absolute maximum ratings parameter s ymbol rating unit note supply voltage v t -0.5 to +4.6 v 1 output short circuit current i o 50 ma ? power dissipation p d 600 mw ? operating temperature t opr 0 to +70 c ? storage temperature t stg -65 to +150 c ? note: 1. the maximum appli cable voltage on any pin with respect to gnd. recommended operating conditions (t a = 0 to +70 c) parameter symbol min. typ. max. unit note supply voltage v cc 2.85 3.0 3.15 v 1 gnd 0 0 0 v 1 input voltage v ih 2.0 ? v cc + 0.3 v ? v il -0.3 ? 0.8 v ? note: 1. the supply voltage with all v cc pins must be on the same l evel. the supply voltage with all gnd pins must be on the same l evel. pin capacitance (t a = 0 to +70 c, f = 1 mhz, v cc = 3.0 v 0.15 v) parameter condi tions symbol min. max. unit input capacitance a 0 - a 17 c in1 ? 8pf uwe, lwe oe, rfsh c in2 ? 8pf ce, cs c in3 ? 8pf input/output capacitance i/o 0 - i/o 15 c out1 ? 10 pf dc electrical chara cteristics (t a = 0 to +70 c, v cc = 3.0 v 0.15 v) parameter symbol cond itions min. max. unit note operating current in normal operation i cc1 trc = t rc (min.) ? 40 ma 1, 2 standby current i cc2 ce , rfsh = v ih (min.) ? 1ma1 ce, rfsh = v cc - 0.2 v ? 30 ma 1 self-refresh average current i cc3 ce = v ih (min.) rfsh = v il (max.) ? 1ma1 ce = v cc - 0.2 v, rfsh = 0.2 v ? 70 ma 1 input leakage current i li 0 v v in 6.5 v 0 v on all other pins -10 10 m a ? output leakage current i lo 0 v v out v cc + 0.3 v input/output pins in high-z state -10 10 m a ? output high voltage v oh i out = -1 ma 2.4 ? v ? i out = -100 m a v cc - 0.2 ? v ? output low voltage v ol i out = 1 ma ? 0.4 v ? i out = 100 m a ? 0.2 v ? data retention voltage v r ? 2.2 3.15 v ? notes: 1. the input/output pins are in h igh impedance st ate. 2. i cc 1 depends on the cycle time. LH5PV16256 cmos 4m (256 16) pseudo-st atic ram 4
ac electrical chara cteristics 1,2,7 (t a = 0 to +70 c, v cc = 3.0 v 0.15 v) parameter symbol min. max. unit notes random read, write cycle time t rc 190 ? ns ? random modify write cycle time t rmw 250 ? ns ? ce pulse width t ce 120 10,000 ns ? ce precharge time t p 60 ? ns ? address setup time t as 0 ? ns 3 row address hold time from ce t rah 30 ? ns 3 column address hold time from ce t cah 120 ? ns ? cs setup time from ce t cs s 0 ? ns ? cs hold time from ce t csh 30 ? ns ? read command setup time t rcs 0 ? ns 11 read command hold time t rch 0 ? ns 9 ce access time t ce a ? 120 ns 4 oe access time t oea ? 60 ns 4 ce to output in low-z t clz 20 ? ns ? oe to output in low-z t olz 0 ? ns ? write disable to output in low-z t wlz 0 ? ns 11 chip disable to output in high-z t chz 030ns ? output disable to output in high-z t ohz 030ns ? we to output in high-z t whz 0 30 ns 9, 13 write command pulse width t wcp 35 ? ns 13 write command setup time t wcs 35 10,000 ns 10, 13 write command hold time t wch 120 10,000 ns 12, 13 data setup time from write disable t ds w 30 ? ns 5, 12, 13 data setup time from chip disable t dsc 30 ? ns 5 data hold time from write disable t dhw 0 ? ns 5, 11, 13 data hold time from chip disable t dhc 30 ? ns 5 data hold time from column address t oh 0 ? ns ? column address hold time from chip disable t ahc 20 ? ns 5 column address hold time from write disable t ahw 0 ? ns 5, 13 transition time (rise and fall) t t 350ns ? output disable setup time t ods 0 ? ns ? output disable hold time t odh 15 ? ns ? refresh time interval (2048 cycle) t ref ? 32 ms 6 auto refresh cycle time t fc 190 ? ns 6 refresh delay time from ce t rfd 90 ? ns ? refresh pulse width (auto refresh) t fap 80 1,000 ns 8 refresh precharge time (auto refresh) t fp 40 ? ns ? ce delay time from refresh enable (auto refresh) t fce 190 ? ns ? refresh pulse width (self refresh) t fas 8,000 ? ns 8 ce delay time from refresh precharge (self refresh) t frs 600 ? ns ? v cc recovery time from data retention t r 5 ? ms ? refresh setup hold time t fs 0 ? ns ? refresh disable hold time t rdh 15 ? ns ? chip disable delay time from rfsh t rdd 15 ? ns ? cmos 4m (256 16) pseudo-static ram lh 5pv16256 5
notes: 1. ac characteristics are measured at t t = 5 ns. 2. ac characteristics are measured at the following condition: 3. row address signals are latched in the memory at the fall ing edge of ce. 4. measured with a load equivalent to 50 pf. 5. input data is latched in the memory at the earl ier rising edge of ce and uwe/ lwe. one of (t ahw , t dsw , t dhw ) and (t ahc , t dsc , t dhc ) needs to be satisfied. the ot her is " dont care." 6. address refresh or auto refresh is needed to be executed 2,048 times within 32 ms. 7. in order to initialize the internal circuits, an initial pause of 500 m s with ce = rfsh = v ih is required after power-up, and followed by at least 8 dummy cycles. when supply voltage falls down below the recommended supply voltage by temporarily power-down, a wai ting time is required at v cc = 0 v for more than 400 ms before power -up, and a pause of 500 m s with ce = rfsh = v ih and 8 dummy cycles are also nece ssary after power-up. 8. auto refresh and self refresh are defined by rfsh pulse width during ce = v ih . if rfsh pulse width is shorter than t fap (max.), the cycle is an auto refresh cycle and m emory cells are refre shed by an internal counter. if rfsh pulse width is longer than t fa s (min.), the cycle is a self refresh cycle and memory cells are refreshed by an internal clock generator automati cally. 9. t rc h and t whz are det ermined by the earlier falling edge of uwe and lwe. 10. t wcs is determined by the later fall ing edge of uwe and lwe. 11. t rcs , t wlz , and t dhw are determined by the later rising edge of uwe and lw e . 12. t wch and t dsw are determined by the earlier rising edge of uwe and lw e . 13. t whz , t wcp , t wcs , t wch , t dsw , t dhw , t wlz , and t ahw should be satisfied by both uwe and lwe. 14. the transition time of the supply voltage in data retention mode is less than 0.05 v/ms. 15. the width of data retention period is more t han t fas (min.) l ike self -ref resh cycle. 16. all input pins are required to be higher than -0.3 v. 17. rfsh must be lower than 0.2 v during the data ret ention period. 18. ce and cs must be higher than v cc - 0.2 v during the data retention period. input 2.2 v 0.8 v 2.4 v 0.4 v 2.0 v 0.8 v 5pv16256s-13 output figure 3. ac characteristics LH5PV16256 cmos 4m (256 16) pseudo-st atic ram 6
t p t csh t p t rc t rdh t rah t cah t rcs t cea t oea t olz t clz column address input row address input valid-data output t ce t css t as t as t rch t chz t ohz t oh i/o 0 - i/o 15 uwe, lwe v ih oe a 0 - a 6 a 7 - a 17 rfsh cs v ih v il ce 5pv16256s-3 v ih v il v ih v il v ih v il v ih v il v il v ih v il v oh v ol figure 4. read cycle cmos 4m (256 16) pseudo-static ram lh 5pv16256 7
t p t csh t p t rc t rdh t rah t cah t wch t ohz t clz column address input row address input t ce t css t as t as t olz t wlz uwe, lwe oe a 0 - a 6 a 7 - a 17 rfsh cs ce 5pv16256s-4 t rdd t ahw t wcs t dsw t wcp t dhw valid-data input t whz t chz i/o 0 - i/o 15 v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol figure 5. write cycle (1) ( oe clock) LH5PV16256 cmos 4m (256 16) pseudo-st atic ram 8
t p t csh t p t rc t rah t cah t wcs column address input row address input t ce t css t as t as t whz uwe, lwe oe a 0 - a 6 a 7 - a 17 rfsh cs ce 5pv16256s-5 t ahc t dsc t dhc valid-data input t clz i/o 0 - i/o 15 v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol figure 6. write cycle (2) ( oe = low , ce control) cmos 4m (256 16) pseudo-static ram lh 5pv16256 9
t p t csh t p t rmw t rdh t rah t cah t rcs t olz t clz column address input row address input valid-data input t ce t css t as t as uwe, lwe oe a 0 - a 6 a 7 - a 17 rfsh cs ce 5pv16256s-6 t dsw t whz t ohz valid-data output i/o 0 - i/o 15 t wcs t wcp t ahc t ahw t dsc t dhw t dhc t cea t oea v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol figure 7. read-m odify-write cycle LH5PV16256 cmos 4m (256 16) pseudo-st atic ram 10
t p t csh t p t rc t rah row address input t ce t css t as a 7 - a 17 rfsh cs ce 5pv16256s-7 i/o 0 - i/o 15 t rch t rdh oe t odh t ods t rcs uwe, lwe note: a 0 - a 6 = don't care v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol open figure 8. address refresh cycle cmos 4m (256 16) pseudo-static ram lh 5pv16256 11
t csh t fap t css t fp rfsh cs ce i/o 0 - i/o 15 note: a 0 - a 17 , uwe, lwe and oe = don't care t rfd t fc t fp t fce t fap open 5pv16256s-8 v ih v il v ih v il v ih v il v oh v ol figure 9. auto refresh cycle t fas t fp rfsh cs ce i/o 0 - i/o 15 note: a 0 - a 17 , uwe, lwe and oe = don't care t fc t frs open 5pv16256s-9 t rfd v ih v il v ih v il v ih v il v oh v ol figure 10. self refresh cycle LH5PV16256 cmos 4m (256 16) pseudo-st atic ram 12
t fp rfsh v cc t rfd t frs note: a o - a 17 , uwe, lwe and oe = don't care 5pv16256s-10 t fs data retention period t r rfsh 0.2 v ce 3 v cc -0.2 v cs 3 v cc -0.2 v cs ce 3.0 v v r v ih v il v ih v il v ih v il figure 11. data retention mode rfsh note: a 0 - a 17 , uwe, lwe and oe = don't care t css 5pv16256s-11 cs ce open t p t rc t rfd t ce t p t csh i/o 0 - i/o 15 v ih v il v ih v il v ih v il v oh v ol figure 12. cs standby mode cmos 4m (256 16) pseudo-static ram lh 5pv16256 13
dimensions in mm [inches] maximum limit minimum limit 44tsop (type ii) (tsop44-p-400) 12.10 [0.476] 11.50 [0.453] 10.40 [0.409] 10.00 [0.394] 11.00 [0.433] 10.60 [0.417] 18.60 [0.732] 18.20 [0.716] 0.12 [0.005] 0.15 [0.006] 0.05 [0.002] 1.20 [0.047] max. 0.125 [0.005] 0.38 [0.015] 0.22 [0.009] 0.80 [0.031] typ. 44 1 44tsop 22 1.10 [0.043] 0.90 [0.035] 23 detail 1.10 [0.043] 0.90 [0.035] 0 - 10 0.15 [0.006] 0.05 [0.002] 0.10 [0.004] 0.15 [0.006] m package diagram 12 120 access time (ns) LH5PV16256 device type s package - ## speed 5pv16256s-12 cmos 4m (256k x 16) pseudo-static ram example: LH5PV16256s-12 (cmos 4m (256k x 16) pseudo-static ram, 120 ns, 44-pin, 400-mil tsop) 44-pin, 400-mil tsop (type ii) (tsop44-p-400) ordering information LH5PV16256 cmos 4m (256 16) pseudo-st atic ram 14

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